This invention relates generally to integrated circuit fabrication and, more particularly, to a method for trimming components of an integrated circuit following its fabrication. The invention refers, as well, to hybrid circuits, assembled board circuits and any other type of electrical circuits that use trimming to adjust performance parameters of the circuit.
Integrated circuit fabrication processes yield circuit devices whose electrical performance is characterized by parameters having a certain range of acceptable values. When the range of fabrication process parameters for these devices results in circuits having functional parameters whose ranges are wider than the specifications allow, it becomes necessary to trim or adjust elements within the integrated circuit, to ensure that the functional parameters for the circuit will meet the specification requirements. Similarly, the components and/or modules included in a circuit may display a range of parameters that may not be tight enough, to meet the overall circuit performance target. This can happen whether or not individual components and/or modules meet their individual specs.
Several circuits and methods are known in the prior art for trimming integrated circuits, exemplary of which are U.S. Pat. No. 4,814,640 to Miyake, U.S. Pat. No. 5,446,407 to Yamamoto, U.S. Pat. No. 5,793,674 to Kubo et al., U.S. Pat. No. 5,991,219 to Nakashima, and U.S. Pat. No. 6,011,425 to Oh et al. The prior art typically involves the use of a non-volatile memory cell, Zener diode zapping, or polysilicon or metal fuse cutting. A common requirement of all of these prior art approaches is that the trimming must be performed on an Automated Test Equipment (ATE) machine. First, the circuit is tested and its parameters are evaluated. If a particular parameter falls outside of its specified range, a first trim bit is adjusted. The parameter is again evaluated on the ATE machine and, if needed, a new trim step is performed, by adjusting another trim bit. This cycle is repeated until the parameter falls within the specified range or until the trim capability is exhausted.
All of the known trim procedures are subject to two major drawbacks. First, trim programming is based on a best guess approach, which is the only option available for the first and all subsequent trimming steps, for each parameter. There is no way of determining circuit performance, following a trim step, without actually performing that trim step. Second, since the entire trim procedure requires the use of an ATE machine, the cost of each integrated circuit is significantly increased, due to the additional ATE test time involved in the trimming procedure. As test cost surpasses actual die cost in many cases, trimming becomes a very important factor in determining the economic viability of an integrated circuit.
In accordance with the preferred embodiments of the present invention, offline trim elements and associated circuitry are provided to minimize the use of an ATE machine during circuit trimming and to thereby reduce production costs significantly. As used herein, the term trim elements refers to fuses, other components and/or subcircuits with substantially similar behavior, Zener diodes, or memory cell based circuits, all of which may be employed to send trim bit high or low voltage signals to circuits requiring trimming. The associated circuitry includes a shift register for converting serially input data into parallel format data, that is afterwards sent to each trim bit. This circuit also serves to temporarily inhibit the effect of the trim elements and sends an arbitrary, externally controlled, digital input signal, to the trim points in the circuit to be trimmed. This circuit includes provisions for permanently disabling itself, following completion of the trimming procedure. When the associated circuitry is disabled, the trim signal is sent to the various trimming points in the circuit to be trimmed, based exclusively on the status of the trim elements themselves.